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SG3525 / KA3525 PWM Controller IC

Rs. 38
DBS175,LS30,TH5,KRT
In stock
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Description

Description:

SG3525 / KA3525 / 3525 PWM CONTROLLER IC / Oscillator

The SG3525A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip 5.1 V reference is trimmed to 1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock.

A single resistor between the CTand the discharge terminals provide a wide range of dead time ad- justment.These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown,as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason,the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525A output stage features NOR logic, giving a LOW output for an OFF state.

Key Features

  1. DUAL SOURCE/SINK OUTPUT DRIVERS
  2. LATCHING PWM TO PREVENT MULTIPLE PULSES
  3. PULSE-BY-PULSE SHUTDOWN
  4. INTERNAL SOFT-START
  5. 8 TO 35 V OPERATION
  6. 100 Hz TO 500 KHz OSCILLATOR RANGE
  7. 5.1 V REFERENCE TRIMMED TO 1 %
  8. ADJUSTABLE DEADTIME CONTROL
  9. INPUT UNDERVOLTAGE LOCKOUT WITH HYSTERESIS
  10. SEPARATE OSCILLATOR SYNC TERMINAL

INTERNAL CIRCUIT DIAGRAM

circuit_diagram_4286_thumbnail.png

 

 

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